Jan Luca Scheerer

Quantitative Technologist @Radix
Previously SWE Intern @CitSec and @Google

Experience

Sep '24 - Present
Amsterdam, NL
Radix Trading LLC
Quantitative Technologist

Core Trading Systems Team
Technical Skills: C++, Quantitative Finance

June '23 – Sep '23
London, UK
Citadel Securities
Software Engineer Intern

Options Technology Team
Technical Skills: C++, Quantitative Finance

May '22 – Sep '22
Zürich, Switzerland
Google
Software Engineer Intern

Worked with Google's Graph Query Language Team
Development of Internal Tooling (Knowledge Graph | PathQuery)
Technical Skills: C++, Relational Algebra, Google Internal Tooling

Feb '22 – Apr '22
Munich, Germany
Software Engineer Intern

End-to-End Implementation of a Classification System
Automatic Generation of Internal & External API-Documentation
Technical Skills: TypeScript, Python3, PyTorch

Education

2022 – 2024
Zürich, Switzerland
Swiss Federal Institute of Technology (ETH Zürich)
MSc. Computer Science, Distinction

  • Major in Data Management Systems, Minor in Machine Learning
  • Cross-Registration at the EPFL, GPA: 6.00/6.00
  • Focus on Systems, Hardware Acceleration, and Algorithms
  • 2024-2024
    Stanford, CA
    Stanford University
    Visiting Student Researcher

  • WARP: An Efficient Engine for Contextualized Multi-Vector Retrieval
  • Courses on Compilers, Operating Systems, and Transformers
  • Stay funded by the German Academic Scholarship Foundation
  • 2018 – 2021
    Munich, Germany
    Technical University Munich (TUM)
    B.Sc. Computer Science, High Distinction

  • Thesis: Time Series Data Mining using Matrix Profiles on FPGAs
  • Focus on C++, Operating Systems, and Computer Architecture
  • Projects

    Time Series Data Mining using Matrix Profiles on FPGAs
    C++, OpenCL, Xilinx Vitis™

    Development of a systolic array-based design to compute the Matrix Profile efficiently on Xilinx FPGAs using C++, OpenCL and Vitis™ High-Level Synthesis for Xilinx FPGAs. The solution scales well with both memory as well as compute resources.

    RISC-V Processor (incl. Instruction Level Pipelining)
    C, Java, VHDL

    Implementation of a processor-core compliant with the RISC-V specification, optimized with an instruction level pipeline. Over the span of two semesters, our team of six students realized the project with the help of the circuit description language VHDL on a FPGA board.

    Cobold Programming Language
    C++, LLVM

    Development of my own strongly typed, low-level, general purpose programming language in C++. Cobold has performance matching C++ using LLVM, with low-level access to bits and addresses.

    leetcode.com (@jlscheerer)
    C++, Java, Python3

    Aiming to solve all leetcode.com (competitive programming) problems.
    Current progress: -/- Easy | -/- Medium | -/- Hard

    Honors & Awards

    German Academic Scholarship Foundation
    Scholarship Holder

    Scholarship of the "Studienstiftung des Deutschen Volkes" awarded in recognition of excellent academic achievements and extracurricular engagement.
    Less than 0.5% of German students are awarded this sholarship.

    TUM: Junge Akademie
    Scholarship Holder

    Scholarship of the "TUM: Junge Akademie" awarded to "exceptionally talented students"
    Selected as one of 42 students for the class of 2020